Layout device and layout method of semiconductor integrated circuit

ABSTRACT

A layout method of a semiconductor integrated circuit includes five steps. The first step is of extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements is carried out. The second step is of generating routing prohibition regions where a routing is prohibited in an area including the wiring crowding place. The third step is of carrying out a routing by bypassing the routing prohibition regions. The fourth step is of deleting the routing prohibition regions. The fifth step is of carrying out a re-routing. The generating step includes: calculating a size and an interval of the routing prohibition regions based on a rate for generating a routing prohibition region in the area in each wiring layer, and generating the routing prohibition regions in the area on the basis of the calculating result.

INCORPORATION BY REFERENCE

This application is based upon and claims the benefit of priority fromJapanese patent application No. 2010-049350 filed on Mar. 5, 2010, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a layout device and a layout method ofa semiconductor integrated circuit, and especially relates to a layoutdevice and a layout method for crowded wiring of a semiconductorintegrated circuit.

2. Description of the Related Art

In accordance with recent advancement of a microfabrication technique,high integration of an LSI is increasingly advanced. In addition,further faster operation is required. In a layout design of the LSI, itis known to carry out routing by using an automatic routing tool. Inorder to satisfy a timing of the high speed operation, the automaticrouting tool carries out the shortest routing. However, volume of thewiring line included in one chip is increased due to the highintegration of the LSI. Accordingly, there is a region such as a cornerof a hard macro where there are many wiring lines whose routing pathsare blocked and which are required to be bypassed and there is a regionwhere wiring lines are crowed such as a wiring region where a high-speedsignal exchange between a plurality of modules intersects. In the regionwhere the wiring lines are crowded, following problems becomeincreasingly prominent. One problem is a routing error caused becauserouting cannot be performed in a routing track completely (for example,short-circuiting or opening of a wiring line, a design rule violationand the like). The other problem is a timing problem that timingdeteriorates because a wiring line is bypassed in order to avoid therouting error.

As a technique for preventing the deterioration of the timing caused bybypass routing, JP2008-227198A (Patent literature 1) discloses a layoutdesign method of a semiconductor integrated circuit. The layout designmethod includes: a step of extracting a wiring crowding region from arequired routing region and from an actually routing allowable regionafter performing placement of circuit elements constituting thesemiconductor integrated circuit; a step of generating a routingprohibition region to the wiring crowding region; a step of carrying outan automatic routing while bypassing the wiring crowding region; and astep of carrying out the automatic routing again after deleting therouting prohibition region. That is, in order to avoid locally crowdedwiring, a routing resource is preliminarily reserved at first by usingthe routing prohibition region. Then, in the initial routing, theautomatic routing is carried out while the routing prohibition region isbypassed. Upon rerouting, the automatic routing is carried out after therouting prohibition region is deleted to release the routing resource.

The inventors have now discovered the following facts. A techniquedisclosed in JP2008-227198A has a problem that the number of routingerrors increases after the automatic routing is carried out while therouting prohibition region is bypassed. For this reason, even when theautomatic routing is carried out again after the routing prohibitionregion is deleted, there will be a problem that the number of theremaining routing errors that could not be corrected completelyincreases in proportion to increase of the routing error andadditionally correction time of the routing error increases. A reasonthat the above-mentioned problem occurs will be described below.

As described above, the technique disclosed in JP2008-227198A firstlyarranges circuit elements, carries out wiring estimation, specifies aregion where wiring lines are crowded, and extracts coordinates coveringthe wiring crowding region. Then, the technique obtains an extensionvalue by calculating the number of wiring lines that run short in thewiring crowding region, and generates the routing prohibition region byadding the obtained extension value to the coordinates covering theextracted wiring crowding region. Subsequently, the technique carriesout the automatic routing so as to bypass the routing prohibitionregion. After that, the technique deletes the routing prohibitionregion, and carries out the rerouting to the reserved routing resource,preferentially applying a wiring line that requires rigid timing. Inthis method, the technique shortens the error correction time for thewiring crowding region, and prevents the timing from deteriorating dueto the bypass routing.

However, the local wiring crowding region is enlarged because ofincrease of a total wiring line amount including wiring lines thatrequire rigid timing due to the high integration and speeding up in therecent LSI. Accordingly, the routing prohibition region for reservingthe routing resource generated in the method disclosed in JP2008-227198Ais naturally enlarged. When the routing prohibition region is enlarged,an amount of the wiring lines bypassing the routing prohibition regionalso increases. As the result, the number of routing errors caused bythe bypassing routing increases, and accordingly there will be problemsthat the routing error cannot be eliminated completely and still remainseven when the rerouting is carried out after deleting the routingprohibition region for reserving the routing resource and that thecorrection time of the routing error increases.

SUMMARY

The present invention seeks to solve one or more of the above problems,or to improve upon those problems at least in part.

In one embodiment, a layout method of a semiconductor integratedcircuit, includes: extracting a wiring crowding place where wiring linesare crowded as compared with a predetermined condition, after carryingout a routing in a region where a placement of circuit elements of thesemiconductor integrated circuit is carried out; generating a pluralityof routing prohibition regions where a routing is prohibited in an areaincluding the wiring crowding place; carrying out a routing,by bypassingthe plurality of routing prohibition regions; deleting the plurality ofrouting prohibition regions after the carrying out routing step; andcarrying out a re-routing after the deleting step. The generating stepincludes: calculating a size and an interval of the plurality of routingprohibition regions based on a rate for generating a routing prohibitionregion in the area in each wiring layer, and generating the plurality ofrouting prohibition regions in the area on the basis of the calculatingresult.

In another embodiment, a tangible computer-readable medium including acomputer program for a layout method of a semiconductor integratedcircuit, including code operable to control a computer, the codeincludes: extracting a wiring crowding place where wiring lines arecrowded as compared with a predetermined condition, after carrying out arouting in a region where a placement of circuit elements of thesemiconductor integrated circuit is carried out; generating a pluralityof routing prohibition regions where a routing is prohibited in an areaincluding the wiring crowding place; carrying out a routing by bypassingthe plurality of routing prohibition regions; deleting the plurality ofrouting prohibition regions after the carrying out routing step; andcarrying out a re-routing after the deleting step. The generating stepincludes: calculating a size and an interval of the plurality of routingprohibition regions based on a rate for generating a routing prohibitionregion in the area in each wiring layer, and generating the plurality ofrouting prohibition regions in the area on the basis of the calculatingresult.

In another embodiment, a layout device of a semiconductor integratedcircuit, includes: a crowding extraction and determination portionconfigured to extract a wiring crowding place where wiring lines arecrowded as compared with a predetermined condition, after carrying out arouting in a region where a placement of circuit elements of thesemiconductor integrated circuit is carried out; a prohibition regiongenerating portion configured to generate a plurality of routingprohibition regions where a routing is prohibited in an area includingthe wiring crowding place; a routing re-estimation portion configured tocarry out a routing by bypassing the plurality of routing prohibitionregions; a prohibition region deletion portion configured to delete theplurality of routing prohibition regions after the routing by bypassingis carried out; and a re-routing portion configured to carry out are-routing after the plurality of routing prohibition regions isdeleted. The prohibition region generating portion includes: aprohibition region calculating portion configured to calculate a sizeand an interval of the plurality of routing prohibition regions based ona rate for generating a routing prohibition region in the area in eachwiring layer, and a prohibition region generating portion configured togenerate the plurality of routing prohibition regions in the area on thebasis of the calculating result.

According to the present invention, even in the case of ahighly-integrated semiconductor integrated circuit, a time for routingin a layout design can be shortened.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description ofcertain preferred embodiments taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a block diagram showing a configuration of a layout device ofa semiconductor integrated circuit according to an embodiment of thepresent invention;

FIG. 2 is a functional block diagram showing a configuration of thelayout device of the semiconductor integrated circuit according to theembodiment of the present invention;

FIG. 3A is a flowchart showing an example of an operation of the layoutdevice of the semiconductor integrated circuit according to theembodiment of the present invention;

FIG. 3B is a flowchart showing an example of an operation of the layoutdevice of the semiconductor integrated circuit according to theembodiment of the present invention;

FIG. 4 is a schematic diagram showing an arrangement of a routingprohibition region generated in the layout method of FIGS. 3A and 3B;

FIG. 5 is a schematic diagram showing an arranging process of routing inthe layout method of FIGS. 3A and 3B;

FIG. 6 is a schematic diagram showing the arranging process of routingin the layout method of FIGS. 3A and 3B;

FIG. 7A is a flowchart showing a procedure (step S4) to createinformation used for generating the routing prohibition region in theflowchart of FIG. 3A;

FIG. 7B is a flowchart showing the procedure (step S4) to create theinformation used for generating the routing prohibition region in theflowchart of FIG. 3A;

FIG. 8 is a schematic diagram describing one example of a generationprocess of the routing prohibition region at step S4 of FIG. 3A;

FIG. 9 is a schematic diagram describing one example of the generationprocess of the routing prohibition region at step S4 of FIG. 3A;

FIG. 10 is a schematic diagram describing one example of the generationprocess of the routing prohibition region at step S4 of FIG. 3A;

FIG. 11 is a schematic diagram describing one example of the generationprocess of the routing prohibition region at step S4 of FIG. 3A;

FIG. 12 is a schematic diagram describing one example of the generationprocess of the routing prohibition region at step S4 of FIG. 3A;

FIG. 13 is a schematic diagram describing an example of elimination of arouting error;

FIG. 14 is a schematic diagram describing the example of elimination ofthe routing error;

FIG. 15 is a schematic diagram describing the example of elimination ofthe routing error; and

FIG. 16 is a schematic diagram describing the example of elimination ofthe routing error.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposed.

Referring to the attached drawings, an embodiment of a layout device anda layout method of a semiconductor integrated circuit of the presentinvention will be described below.

A configuration of the layout device of the semiconductor integratedcircuit according to the embodiment of the present invention will bedescribed. FIG. 1 is a block diagram showing the configuration of thelayout device of the semiconductor integrated circuit according to theembodiment of the present invention. The layout device 10 is aninformation processing device exemplified by a computer, and includes anoperation processing device 1, a first storage device 2, a secondstorage device 3, a library database 4, an output device 5, and an inputdevice 6. These are connected so as to be able to send and receiveinformation with each other through a bus and a cable.

The first storage device 2 stores layout data such as LSI logical designdata, LSI physical design data, STA (Static Timing Analysis) restrictiondata, a routing prohibition region information list, and the like. Thesecond storage device 3 stores a layout program describing a layoutmethod such as a logical circuit placement process procedure, an outlinerouting process procedure, a routing prohibition region generationprocedure, a detail routing process procedure, and the like. The librarydatabase 4 stores: a timing library; and a library including a logicalcircuit diagram net wiring information, a chip shape and the like. Thefirst storage device 2, the second storage device 3, and the librarydatabase 4 are exemplified by an electronic device such as a ROM (ReadOnly Memory), a RAM (Random Access Memory), a flash memory, a HDD (HardDisk Drive) and the like, or by a combination of them. Meanwhile, adevice for reading information (the above-mentioned data and program),which is recorded in a computer readable storage medium, that is, anoptical disk such as a CD-ROM and a DVD, a magnetic disk, a magnetictape, a semiconductor memory and others, from the storage medium may beemployed.

The operation processing device 1 carries out the process of the layoutprogram stored in the second storage device 3 by using data stored inthe first storage device 2 and the library data base 4. The operationprocessing device 1 is exemplified by a CPU (Central Processing Unit)and the peripheral circuit (for example, a RAM (Random Access Memory) asa main memory).

The output device 5 outputs data of: an outline routing diagram; adetail routing diagram; and the like created by the operation processingdevice 1. The output device is exemplified by a display and a printer.

The input device 6 outputs data generated by a user's operation to theoperation processing device 1 and the like. The input device isexemplified by a keyboard and a mouse.

FIG. 2 is a functional block diagram showing a function of the layoutdevice of the semiconductor integrated circuit according to theembodiment of the present invention. The layout device 10 includes anoutline routing portion 11, a wiring crowding degree extraction portion12, a wiring crowding degree determination portion 13, an inputinformation creating portion 14, a routing prohibition regioninformation generation portion 15, a routing prohibition regioninformation processing portion 16, an outline routing re-estimationportion 17, a routing prohibition region deletion portion 18, a detailrouting portion 19, a routing error determination portion 20, a routingprohibition region condition changing portion 21, and an inputinformation determination portion 22. The above-mentioned layoutprograms are installed in the above-described information processingdevice exemplified by the computer, and thus functions of the outlinerouting portion 11 to the input information determination portion 22 arerealized.

The outline routing portion 11 carries out an outline routing after anautomatic placement of logical circuits (cells, modules, macros and thelike) is carried out based on a commonly-known method. The wiringcrowding degree extraction portion 12 extracts a wiring crowding degreein each partial region from a result of the outline routing by theoutline routing portion 11. The wiring crowding degree determinationportion 13 determines whether a partial region with a high wiringcrowding degree exists or not based on the wiring crowding degreesextracted by the wiring crowding degree extraction portion 12. Theoutline routing portion 11, the wiring crowding degree extractionportion 12, and the wiring crowding degree determination portion 13 canbe regarded as a crowding extraction and determination portion 25 whichextracts a wiring crowding region where wiring lines are crowded morethan a preliminarily set condition after the placement of the circuitelements and routing of the semiconductor integrated circuit.

The input information creating portion 14 creates input information F01used for generating a routing prohibition region regarding the regiondetermined as the region with high wiring crowding degree. The routingprohibition region information generation portion 15 creates routingprohibition region generating information F02 used for reserving arouting resource by using the input information F01 created by the inputinformation creating portion 14 as an input. The routing prohibitionregion information processing portion 16 generates the routingprohibition region by using the routing prohibition region generatinginformation F02 generated by the routing prohibition region informationgeneration portion 15 as an input. The input information creatingportion 14, the routing prohibition region information generationportion 15, and the routing prohibition region information processingportion 16 can be regarded as a prohibition region generating portion 26for generating a plurality of routing prohibition region where a routingis prohibited in the region including the wiring crowding region.

The outline routing re-estimation portion 17 carries out re-estimationof the outline routing (path), considering the routing prohibitionregion generated by the routing prohibition region informationprocessing portion 16. The routing prohibition region deletion portion18 deletes the routing prohibition region generated by the routingprohibition region information processing portion 16. In the case wherethe wiring crowding degree is determined to be low by the wiringcrowding degree determination portion 13, the detail routing portion 19carries out the detail routing. The routing error determination portion20 determines whether the routing error is eliminated and the routing iscompleted or not after the detail routing portion 19 carries out thedetail routing process. In the case where the routing errordetermination portion 20 determines that the routing error remains andthe routing is not completed, the routing prohibition region conditionchanging portion 21 changes a condition to generate a routingprohibition region in order to increase a routing resource in each oneregion. The input information determination portion 22 determineswhether or not the condition to generate the routing prohibition regionchanged by the routing prohibition region condition changing portion 21satisfies the input information F01. Specific functions and operationswill be described below.

Next, an operation (a layout method) of the layout device of thesemiconductor integrated circuit according to the embodiment of thepresent invention will be described below. FIGS. 3A and 3B areflowcharts showing one example of the operation (the layout method) ofthe layout device of the semiconductor integrated circuit according tothe embodiment of the present invention. FIGS. 4 to 6 are schematicdiagrams showing one example of: arrangement of the generated routingprohibition region; and an arranging process of the routing in thelayout method of FIGS. 3A and 3B. In FIGS. 4, 5 and 6, the semiconductorintegrated circuit 50 includes a hard macro region (RAM, ROM and thelike) 100 and functional modules M1 to M3. There is a wiring crowdingregion 200, a region where wiring lines are crowded, at a corner of andin the vicinity of the hard macro region 100. An area 600 made byexpanding a periphery of the wiring crowding region 200 to its outsideincludes an area 601, a lattice 602, routing prohibition regions 300 a,and wiring lines N1 to N5. The area 601 includes the wiring crowdingregion 200, and is an area where the routing prohibition region isgenerated in the present embodiment. The lattice 602 is a latticeindicating the minimum routing unit (one grid) of a single routing trackfor a wiring line of a wiring layer that is an object of the routingprohibition. The routing prohibition region 300 a is a region where therouting is prohibited. Meanwhile, in FIGS. 4 to 6, a wiring line in avertical direction of the drawings is a wiring line in a Y direction,and a wiring line in a horizontal direction of the drawings is a wiringline in an X direction.

Using the examples of FIGS. 4 to 6, the flowcharts of FIGS. 3A and 3Bwill be described. However, the respective steps described below areprocesses carried out in cooperation between: the layout program in thesecond storage device 3; and the operation processing device 1 in thecomputer system shown in FIG. 1. As for the data to be inputted and thedata to be outputted at the respective steps, the input and output arecarried out by the first storage medium 2, the library database 4, theinput device 6, and the output device 5.

(1) Step S1:

At first, based on a commonly-known method, an automatic placementprocess of logical circuits (cells, modules, macros and the like) iscarried out. The outline routing portion 11 carries out outline routingafter the completion of the automatic placement process. The outlinerouting is a process described below. Specifically, the inside of arouting region is roughly separated into a plurality of segments atfirst. Then, each of the plurality of segments is separated into aplurality of partial regions called an outline lattice. After that, inorder to check which partial region each of all nets pass through, theoutline paths are obtained, admitting routing errors to some extent. Theoutline routing portion 11 generates a routing report. The routingreport describes: a routing error occurrence coordinate and a wiringlayer where an error occurs; or the number of routing errors and anerror occurrence rate in each of the wiring layers in the whole of therouting region.

(2) Step S2:

The wiring crowding degree extraction portion 12 extracts the wiringcrowding degree in each of the partial regions from the result of theoutline routing at step S1. For example, the partial region may be theoutline lattice, and may be a region including a plurality of theoutline lattices. In addition, the partial region may be a region thatthe outline lattice is minutely separated. When the outline lattice isminutely separated, focusing of the wiring crowding region can be easilyrealized; however, an extraction time will be increased. The wiringcrowding degree is a ratio of the number of the wired wiring lines tothe number of the routing tracks included in the routing region. Forexample, in each of the wiring layers in the partial region, the wiringcrowding degree can be extracted by dividing the number of thepresently-wired wiring lines by the number of the routing tracks (thepossible number of the wiring lines to be wired).

(3) Step S3:

The wiring crowding degree determination portion 13 determines whetherthe region with high wiring crowding degree exists or not based on thewiring crowding degrees extracted at step S2. For example, asdetermination criteria, in the case where the wiring crowding degreeexceeds 100%, the region is determined to be the region with high wiringcrowding degree since the number of wiring lines is larger than thepossible number of the wiring lines to be wired. However, if it can bedetermined that the routing is difficult because of dependency on aprocess and a design even though the degree falls below 100%, it may beappropriately determined whether or not the region is the region withhigh wiring crowding degree, with consideration for the dependency.

In the case where the region is determined to be the region with lowwiring crowding degree (step S3: No), the flow proceeds to step S10, andthe detail routing is carried out. In the case where the region isdetermined to be the region with high wiring crowding degree (step S3:Yes), the flow proceeds to step S4, and the information for generatingthe routing prohibition region is generated.

(4) Step S4:

To the region determined as the region with the high wiring crowdingdegree at step S3, the routing prohibition region information generationportion 15 (and the input information creating portion 14) generates therouting prohibition region generating information F02 used forgenerating the routing prohibition region. The process of step S4 (stepsS5 to S6) will be described below.

(5) Step S5:

To the region determined as the region with the high wiring crowdingdegree, the input information creating portion 14 creates the inputinformation F01 used for generating the routing prohibition region.

(6) Step S6:

The routing prohibition region information generation portion 15generates the routing prohibition region generating information F02 forreserving the routing resource by using the input information F01 as aninput. The routing prohibition region generating information F02 isinformation indicating how to generate a plurality of routingprohibition regions (a predetermined condition for generating therouting prohibition region) to the region determined as the region withthe high wiring crowding degree, and designating a size of the routingprohibition region and an arrangement place of the routing prohibitionregion.

(7) Step S7:

The routing prohibition region information processing portion 16generates the routing prohibition region by using the routingprohibition region generating information F02 created at step S4 (stepS5+step S6) as an input.

FIG. 4 shows an example of generating the routing prohibition region. InFIG. 4, there is the routing crowding region 200 that is the region withthe high wiring crowding degree at the corner of and in the vicinity ofthe hard macro region 100. The area 600 includes the wiring crowdingregion 200, and is made by expanding the periphery of the wiringcrowding region 200 to its outside. In the area 600, the routingprohibition region information processing portion 16 generates therouting prohibition regions 300 a in the area 601, which is prepared forgenerating routing prohibition regions, by using the routing prohibitionregion generating information F02 created at step S4 as an input.

(8) Step S8:

The outline routing re-estimation portion 17 carries out there-estimation of the outline routing (path), with consideration for therouting prohibition region 300 a generated at step S7.

FIG. 5 shows a state after the re-estimation of the outline routing iscarried out in the area 600. The region between the routing prohibitionregions 300 a is used as the routing region. A wiring line that cannotbe applied within the area 601 where the routing prohibition, regions300 a are generated is wired outside the area 601. However, in theprocess of the outline routing, since the timing is considered, therouting is carried out while the routing error remains even when thereis a place where the routing track runs short. Each place rounded by anellipse in FIG. 5 shows a routing error place. In one routing errorplace, two wiring lines of the wiring line N1 and the wiring line N2 arewired in one routing track, which shows a state where the routing errorstill remains. Similarly, in the other routing error place, two wiringlines of the wiring line N3 and the wiring line N5 are wired in onerouting track, which shows a state where the routing error stillremains.

(9) Step S9:

The routing prohibition region deletion portion 18 deletes the routingprohibition regions 300 a generated at step S7. Then, the flow returnsto step S2 again, and the extraction of the wiring crowding degree iscarried out. A series of the processes at steps S2 to S9 are repeateduntil the region with the high wiring crowding degree disappears.

(10) Step S10:

In the case where the region is determined as the region with the lowwiring crowding degree at step S3, the detail routing portion 19 carriesout the detail routing. The detail routing is a process for: furtherminutely segmenting the outline lattice into lattices, each latticebeing composed of a single grid (single grid lattice) ; obtaining thedetail path of each of all nets o the basis of which single grid latticethe net passes through; and correcting the wiring line that violates thedesign rule.

FIG. 6 shows a state after the detail routing is carried out in the area600. In FIG. 6, the routing prohibition regions 300 a have been deletedat step S9, and thus can be used as the routing region. The routingerrors between the wiring line N1 and the wiring line N2 and between thewiring line N3 and the wiring line N5 that has occurred by routing inthe same wiring layer of the same grid in FIG. 5 can be restored bymoving the wiring line N1 and the wiring line N5 to the routing regiongenerated in FIG. 6 when the routing prohibition region 300 a has beendeleted. In addition, since the routing region that can be used bydeleting the routing prohibition region 300 a is reserved in thevicinity of the routing error occurrence places, the routing error canbe corrected without generating the bypassing of the wiring line.

(11) Step S11:

After the process of the detail routing at step S10 is carried out, therouting error determination portion 20 determines whether or not therouting error is eliminated and whether or not the routing error isrestored. In the case where it is determined that the routing error isrestored (step S11: Yes), the flow proceeds to step S15, and thus therouting process is completed. In the case where it is determined thatthe routing error still remains and that the routing error is notrestored (step S11: No), the flow proceeds to step S12, and thus acondition of generating the routing prohibition region is changed.

However, in the case where the routing error still remains, when it canbe determined that the number of the routing errors is a predeterminednumber (for example, a few places) or less and can be restored by asimple correction without the automatic routing tool, the error may bedetermined to be restored, the flow may proceed to step S15 to completethe routing.

(12) Step S12:

In the case where it is determined that the routing error has not beenrestored at step S11, it can be determined that the routing resourcereserved by the routing prohibition region 300 a generated in the seriesof processes of steps S2 to S9 is not the most suitable. Accordingly,the routing prohibition region condition changing portion 21 (and theinput information determination portion 22) changes a condition ofgenerating the routing prohibition region at step S12. Then, the flowreturns to step S4 (S5+S6) and the routing prohibition region generatinginformation F02 is created again. After that, until the routing errordisappears in the determination at step S11, the flow returns from stepS12 to step S4 and then the flow carrying out step S4 to step S11 isrepeated. The process at step S12 (steps S13 to S14) will be describedbelow.

(13) Step S13:

In the case where the routing error is not restored at step S11, therouting prohibition region condition changing portion 21 changes thecondition for generating the routing prohibition region in order toincrease the routing resource at each one place.

(14) Step S14:

The input information determination portion 22 determines whether or notthe condition for generating the routing prohibition region that waschanged at step S13 satisfies the input information F01 outputted atstep S5. In the case where the changed condition for generating therouting prohibition region does not satisfy the input information F01(step S14: No), the flow returns to step S5 and then the inputinformation F01 is created again. In the case where the changedcondition for generating the routing prohibition region satisfies theinput information F01 (step S14: Yes), the flow returns to step S6 andthen the routing prohibition region generating information F02 iscreated again.

Next, details of the process at step S4 in the flowchart according tothe present embodiment of FIG. 3A will be described. FIGS. 7A and 7B areflowcharts showing the procedure (step S4) to create the information forgenerating the routing prohibition region in the flowchart of FIG. 3A.FIGS. 8 to 12 are schematic diagrams describing one example of thegeneration process of the routing prohibit ion region at step S4 of FIG.3A. FIGS. 8 to 12 show the area 601 where the routing prohibition regionin FIGS. 4 to 6. However, FIGS. 8 and 9 are also views describingexamples of respective variables. In this case, FIG. 8 shows variablesof a calculation initial step, and FIG. 9 shows: variables outputted asa calculation result; and an example of the generation of the routingprohibition region.

(5) Step S5:

At first, the input information creating portion 14 creates the inputinformation F01 used for generating the routing prohibition region. Theinput information creating process is separated into two processes of:determination of basic input information F011 (step S51); anddetermination of additional input information F012 (step S52). Step S51and step S52 will be described below.

(51) Step S51:

The input information creating portion 14 creates the basic inputinformation F011 and outputs the information F011. The basic inputinformation F011 shows: information (a) of an area where the routingprohibition is generated; information (b) of the wiring layer that is anobject of the routing prohibition; and information (c) of a generationrate (%) at which the routing prohibition is generated. The information(a) to (c) is determined on the basis of: the routing report in theoutline routing at step S1; the wiring crowding degree in each partialregion extracted at step S2; and the like. Specific description is asfollows.

The information (a) of the area where the routing prohibition isgenerated specifies bottom-left and top-right coordinates, for example,so as to include an area whose wiring crowding degree in each partialregion extracted at step S2 exceeds 100%. Moreover, in the case wherethe regions exceeding 100% are continuously generated in the X directionand in the Y direction, the regions continuously exceeding 100% areregarded as one group. Then, the minimum value and maximum value of theX coordinate and the minimum value and maximum value of the Y coordinateamong a coordinate group of the one group are obtained. After that, thearea including: the bottom-left coordinate (the X coordinate minimumvalue and the Y coordinate minimum value); and the top-right coordinate(the X coordinate maximum value and the Y coordinate maximum value) isspecified.

The information (b) of the wiring layer that is an object of the routingprohibition can be generated by extracting a routing error layer, forexample, in the routing error occurrence coordinate on the basis of therouting report generated at step S1.

The information (c) of the generation rate (%) of the routingprohibition region is a value indicating the required extent of therouting prohibition region (corresponding to an amount of the routingresource) in reserving the routing resource by deleting the routingprohibition region at step S9. That is, the information (c) is a ratioof the routing prohibition region 300 a generated in the area 601 basedon the wiring crowding degree. For example, in the region with the highwiring crowding degree determined at step S3, the value can be obtainedon the basis of a ratio of the number of wiring lines with the routingerrors (for example, “the number of wiring lines with the routingerrors”/“the number of actually-wired wiring lines”), when the routingis carried out in the region, in which the number of wiring lines islarger than the number of the routing tracks in the routing report atstep S1.

(52) Step S52:

The input information creating portion 14 creates the additional inputinformation F012 and outputs the information F012. The additional inputinformation F012 shows: information (d) of the minimum number of wiringlines able to pass through between the adjacent routing prohibitionregions in the wiring layer that is an object of the routing prohibitionwithin an area where the routing prohibition is generated; information(e) of the minimum number of wiring lines able to pass through betweenthe adjacent routing prohibition regions in a different routingdirection from a routing direction of the wiring layer that is an objectof the routing prohibition; and information (f) of a generation rate (%)at which the routing prohibition is generated in the same direction asthat of the case of the information (e). For example, if the wiringlayer that is an object of the routing prohibition is in the Ydirection, the information (d) is information of the number of wiringlines in the Y direction, the information (e) is information of thenumber of wiring lines in the X direction, and the information (f) isinformation of the routing prohibition region with respect to the wiringline in the X direction. On this occasion, the information of therouting prohibition region with respect to the wiring line in the Ydirection is the information (c). The information (d) to (f) isdetermined on the basis of: the routing report in the outline routing atstep S1; the wiring crowding degree in each partial region extracted atstep S2; and the like. Specific description is as follows.

The information (d) of the minimum number of wiring lines able to passthrough between the adjacent routing prohibition regions may specify theminimum unit “1”; or the information may be determined on the basis ofthe way how the wiring line passes in the routing error occurrenceregion interfered by the area (a) where the routing prohibition regionis generated. FIGS. 9 to 12 show the generation state of the routingprohibition region which differs on the basis of the minimum number ofthe wiring lines. For example, in the case where the routing prohibitionregion is generated between the modules connected to each other with tenwiring lines that have rigid timing and that are required to be wired inthe shortest path, the information is set to the minimum number (d) ofthe wiring lines in which the routing prohibition regions are gatheredas shown in FIG. 12 enabling to reserve the routing resources for tenwiring lines after the routing prohibition regions are deleted.Additionally, in the case where the routing prohibition region isgenerated in an region where the wiring lines pass through in variousdirections, the information is set to the minimum number (d) of thewiring lines in which the routing prohibition regions are scattered asshown in FIG. 9 enabling to sparsely reserve the routing resources afterthe routing prohibition regions are deleted.

Moreover, in the case of a different routing direction from the routingdirection of the wiring layer, the information (e) of the minimum numberof the wiring lines able to pass through between the adjacent routingprohibition regions may also specify the minimum unit “1” in the samereason as that of (d); or the information may be determined on the basisof the way how the wiring line passes in the routing error occurrenceregion interfered by the area (a) where the routing prohibition regionis generated.

For example, in the same reason as that of (c), the information (f) ofthe generation rate at which the routing prohibition is generated can beobtained on the basis of a ratio of the number of wiring lines with therouting errors (for example, “the number of wiring lines with therouting errors”/“the number of actually-wired wiring lines”), when therouting is carried out in the region, in which the number of wiringlines is larger than the number of the routing tracks in the routingreport at step S1.

Here, a reason for considering both of the X direction and Y directionis as follows. Even if the wiring layer of the routing prohibitionobject is in the Y direction, the rule is not always kept when therouting is carried out in the region of the high wiring crowding degree.If an error regarding the DRC (Design Rule Checking), the LVS (LayoutVersus Schematics) and the like does not occur, one of the verticaldirection and horizontal direction in the identical layer is switched tothe other in some cases. For this reason, the reservation of resourcesin both of the X direction and Y direction can be considered.

In addition, the basic input information F011 is essential inputinformation, but the additional input information F012 is not essentialinput information. In the case where an index for designating the extentof a size and interval of the routing prohibition region to be generatedare already given by the designer, a carrying-out time can be shortenedby setting the additional input information F012. In the case where theadditional input information F012 is not specified, the size andinterval of the routing prohibition region are set as the minimumvalues, and thus the change values in the condition changing process(step S12) of generating the routing prohibition region in the flow ofFIG. 3B are the minimum values. Accordingly, a repetition count of theflow may be increased. However, in the case where the additional inputinformation F012 is specified, starting values of the size and intervalof generating the routing prohibition region start from the middle.Accordingly, since the number of conditions in the condition changingprocess of the routing prohibition region is reduced, the repetitioncount can be reduced.

(6) Step S6:

The routing prohibition region information generation portion 15generates the routing prohibition region generating information F02 forreserving the routing resource by using the basic input information F011and the additional input information F012 as inputs. The routingprohibition region generating information generation process at step S6is carried out in the process at steps S61 to S611. Steps S61 to S611will be described below.

(6-1) Step S61:

The total number La111 of all routing tracks allowing the routing in thewiring direction of the wiring layer (the wiring layer that is an objectof the routing prohibition) specified by the information (b) iscalculated in the whole of the region specified by the coordinates ofthe information (a) of the basic input information F011 (the area wherethe routing prohibition is generated).

Using FIG. 8, a calculation procedure of the total number La111 ofrouting tracks is shown. The information (a) of the area where therouting prohibition is generated sets the bottom-left coordinate (X1,Y1) of the area 601 and the top-right coordinate (X2, Y2) of the area601. The information (b) of the wiring layer that is an object of therouting prohibition sets a wiring layer as a second layer and as awiring layer where the routing in the Y direction is carried out. Alength in the X direction is obtained from the bottom-left coordinate(X1, Y1) and top-right coordinate (X2, Y2) of the range 601. When a gridsize of one routing track in the wiring layer of the

Y routing that is an object of the routing prohibition is assumed to beZ, the total number La111 of the routing tracks is calculated byEquation (1).

La111=(X2−X1)/Z:   Equation (1)

FIG. 8 shows that twenty routing tracks, each extending toward the Ydirection, are included.

(6-2) Step S62

In the region specified by the coordinates of the information (a) of thebasic input information F011 (the area where the routing prohibition isgenerated), the routing prohibition region is generated at a generationrate (the generation rate at which the routing prohibition is generated)specified by the information (c) toward the routing direction of thewiring layer (the wiring layer that is an object of the routingprohibition) specified by the information (b), and the maximum numberLmax1 of the wiring lines able to be wired in the routing direction ofthe wiring layer (the wiring layer that is an object of the routingprohibition) specified by the information (b) in the region where therouting prohibition region is not generated is calculated.

Using FIG. 8, a calculation procedure of the number Lmax1 of the wiringlines is shown. The information (c) of the generation rate (%) at whichthe routing prohibition is generated is assumed to be the generationrate Psnt1 of 60% (the generation rate Psnt1=60%), and thus the 60% ofthe routing in the Y direction is prohibited. The length of the area 601in the X direction is assumed to be 1 (=100%), and the value of thegeneration rate Psnt1=60(%) at which the routing prohibition region 300is generated is subtracted from 1. When this value is multiplied by theactual length of the area 601 in the X direction, the remaining lengthobtained by subtracting the actual length of the generated routingprohibition region 300 from the actual length of the area 601 in the Xdirection is obtained. On this occasion, a grid size (e.g., a width) ofone routing track in the wiring layer of the Y routing is Z, andaccordingly the number Lmax1 of the wiring lines is calculated byEquation (2).

Lmax1=(X2−X1)×(1−Psnt1/100)/Z:   Equation (2)

FIG. 8 shows that the total number Lmax1 of the routing tracks is“20×(1−0.6)=8”, that is, eight wiring lines can be wired to twentyrouting tracks in the Y direction (the routing in the remaining twelverouting tracks is prohibited).

(6-3) Step S63:

Using the information (d) of the additional input information F012, thepossible division number for insertion of the routing prohibition regionis calculated with respect to the maximum number of the wiring lines(Lmax1) that can be wired in the Y direction, the maximum number beingcalculated at step S62.

As shown at step S61, since the routing direction is the Y direction,the information (d) is the minimum number Lmin1 of the wiring lines tobe wired in the Y direction between the adjacent routing prohibitionregions. The possible division number Lmax1B for insertion of therouting prohibition region is calculated by dividing the maximum numberLmax1 of the wiring lines that can be wired in the Y direction by theminimum number Lmin1 of the wiring lines to be wired in the Y directionbetween the adjacent routing prohibition regions. The calculationEquation is shown as the following Equation (3).

Lmax1B=Lmax1/Lmin1:   Equation (3)

FIG. 8 shows that the minimum number Lmin1 is assumed to be one (theminimum number Lmin1=1) and the routing track is a track where onewiring line can be wired in the Y direction, and that the number Lmax1of the wiring lines equal to eight (the number Lmax1 of the wiringlines=8) can be divided into “Lmax1B=8/1=8” (eight).

(6-4) Step S64:

The number Lext1 of the wiring lines that are prohibited to be wired inthe area specified by the information (a) of the basic input informationF011 is calculated by subtracting the maximum number Lmax1 of the wiringlines that can be wired and obtained at step S62 from the total numberLa111 of the routing tracks obtained at step S61. The calculationEquation is shown as the following Equation (4).

Lext1=La111−Lmax1:   Equation (4)

FIG. 8 shows that the number Lext1 of the wiring lines that areprohibited to be wired is equal to “20−8=12” and the number Lext1corresponds to a width of the routing prohibition region 300 generatedin the X direction.

(6-5) Step S65:

The number Lext1 of the wiring lines that are prohibited to be wired,the number being obtained at step S64, is divided by the possibledivision number Lmax1B obtained at step S63, and thus the number SLext1of the prohibited wiring lines included in the one division iscalculated. The calculation Equation is shown as the following Equation(5).

SLext1=Lext1/(Lmax1B−1):   Equation (5)

FIG. 9 shows that the number SLext1 of the prohibited wiring linesincluded in the one division is equal to “12/(8−1)=1.7≈2” and that thesize (e.g., a width) in the X direction of the routing prohibitionregion 301 generated by dividing the region in the X direction is tworouting tracks.

Subsequently, an operation procedure (step S66 to 5610) of a differentdirection (the Y direction in the example of FIG. 4) from the routingdirection specified by the information (b) of the basic inputinformation F011 in the same wiring layer as that at steps S61 to S65will be described. At steps S66 to 5610, the calculation method is thesame as the steps S61 to S65 described above.

(6-6) Step S66:

Using the coordinates ((X1, Y1), (X2, Y2)) of the information (a) of thearea where the routing prohibition is generated in the basic inputinformation F011 and the grid size Z of one routing track, the totalnumber La112 of the routing tracks in the X direction is calculated byEquation (11).

La112=(Y2−Y1)/Z:   Equation (11)

FIG. 8 shows that twenty routing tracks, each extending toward the Xdirection are included.

(6-7) Step S67:

Using the coordinates of the information (a) of the basic inputinformation F011 and the generation rate Psnt2 (here 50%) specified bythe information (f) of the generation rate (%) at which the routingprohibition is generated in a different routing direction from therouting direction of the wiring layer that is an object of the routingprohibition of the additional input information F012, the maximum numberLmax2 of wiring lines able to be wired in the X direction when therouting prohibition region is generated is calculated by Equation (12).

Lmax2=(Y2−Y1)×(1−Psnt2/100)/Z:   Equation (12)

FIG. 8 shows that the total number Lmax2 of the routing tracks is“20×(1−0.5)=10”, that is, ten wiring lines can be wired to the twentyrouting tracks in the X direction (the routing in the remaining tenrouting tracks is prohibited).

(6-8) Step S68:

Using the minimum number Lmin2 of the wiring lines to be wired in the Xdirection between the adjacent routing prohibition region in theinformation (e) of the additional input information F012, the possibledivision number Lmax2B for insertion of the routing prohibition regionis calculated, with respect to the maximum number Lmax2 of the wiringlines able to be wired in the X direction obtained at step S67, byEquation (13).

Lmax2B=1 max2/Lmin2:   Equation (13)

FIG. 8 shows that the minimum number Lmin2 is assumed to be one (theminimum number Lmin2=1) and the routing track is a track where onewiring line can be wired in the X direction, and that the number Lmax2of the wiring lines equal to ten (the number Lmax2=10) can be dividedinto “Lmax2B=10/1=10” (ten).

(6-9) Step S69:

By subtracting the maximum number Lmax2 of the wiring lines obtained atstep S67 from the total number La112 of the routing tracks in the Xdirection obtained at step S66, the number Lext2 of the wiring linesthat are prohibited to be wired in the area specified by the information(a) of the basic input information F011 is calculated by the followingEquation (14).

Lext2=La112−Lmax2:   Equation (14)

FIG. 8 shows that the number Lext2 of the wiring lines that areprohibited to be wired in the X direction is equal to “20−10=10” and thenumber Lext2 corresponds to a width of the routing prohibition region300 generated in the Y direction.

(6-10) Step S610:

The number Lext2 of the wiring lines that are prohibited to be wired,the number being obtained at step S69, is divided by the possibledivision number Lmax2B obtained at step S68, and thus the number SLext2of the prohibited wiring lines included in the one division iscalculated by the following Equation (15).

SLext2=Lext2/(Lmax2B−1):   Equation (15)

FIG. 9 shows that the number SLext2 of the prohibited wiring linesincluded in the one division is equal to “10/(10−1)=1.1≈1” and that thesize (e.g., a length) in the Y direction of the routing prohibitionregion 301 generated by dividing the region in the Y direction is onerouting track.

(6-11) Step S611:

The routing prohibition region generating information F02 is created onthe basis of the basic input information F011, the additional inputinformation F012, and the calculation results at steps S61 to S610. Atfirst, the numbers SLext1 (Y direction) and SLext2 (X direction) of theprohibited wiring lines in the one division and the minimum numbersLmin1 (Y direction) and Lmin 2 (X direction) of the wiring lines wiredbetween the routing prohibition region are respectively multiplied bythe one grid size Z of the wiring layer to be an object, thereby beingchanged into the width of the routing track. Then, the coordinateinformation is created. The coordinate information indicates data of therectangles of the routing prohibition regions to be arranged atintervals of Lmin1×Z in the X direction and Lmin2×Z in the Y direction.The rectangle has the size of SLext1×Z in X direction and the size ofSLext2×Z in Y direction when the wiring layer is in the X direction. Theinformation of the wiring layer is added to the created coordinateinformation, and the information is outputted as the routing prohibitionregion generating information F02.

Next, referring to FIGS. 9 to 12, details of the process at step S12 inthe flowchart according to the embodiment of FIG. 3B will be described.

FIGS. 9 to 12 show examples of results obtained by, when it isdetermined at step S11 that the routing error is not restored (step S11:No), carrying out again the series of processes at steps S4 to S11 afterchanging the routing prohibition region generation condition.

(13) Step S13:

In the case where it is determined at step S11 that the routing error isnot restored (step S11: No), the reservation number of the routingresources is changed to be improved by increasing the number of theminimum numbers Lmin1 (Y direction) and Lmin2 (X direction) of thewiring lines to be wired between the adjacent routing prohibitionregions. The increase of the minimum number of the wiring lines to bewired between the routing prohibition regions is carried out by settingthe minimum number Lmin1 and Lmin2 of the wiring lines again as theincrement number Cnt1 of the wiring lines in the Y direction and theincrement number Cnt2 of the wiring lines in the X direction. Thecalculation equations are shown as the following Equations (6) and (16).

Lmin1=Lmin1+Cnt1:   Equation (6)

Lmin2=Lmin2+Cnt2:   Equation (16)

On this occasion, the processes (S13 to S14 and S4 to S11) after stepS13 are repeated until it is determined that the routing error isrestored at step S11. As for the increment numbers Cnt1 and Cnt2 of thewiring lines to be set at step S13, the minimum unit of the incrementnumber Cnt1 of the wiring lines in the Y direction is set to one sincethe routing direction of the embodiment is the Y direction; however, thenumbers may be set to two or more in consideration of the repetitioncount of the case where the total number of the routing tracks or awiring line amount are large. The increment number Cnt2 of the wiringlines in the X direction different from the routing direction is set tozero or more.

(14) Step S14:

As described above, the processes (S13 to S14 and S4 to S11) after stepS13 are repeated until it is determined at step S11 that the routingerror is restored.

As the result of setting again the minimum numbers Lmin1 (the Ydirection) and Lmin2 (the X direction) of the wiring lines to be wiredbetween the routing prohibition regions at step S13, it is determinedwhether or not the number exceeds the values of the maximum numbersLmax1 (the Y direction) and Lmax2 (the X direction) of the wiring linesthat can be wired, the maximum numbers being calculated at step S62 andstep S67. In the case of not exceeding the values of the maximum numbersLmax1 (the Y direction) and Lmax2 (the X direction) (step S14: Yes), theflow proceeds to step S6, and re-calculation of the routing prohibitionregion generating information is carried out by using the values of theminimum numbers Lmin1 (the Y direction) and Lmin2 (the X direction) ofthe wiring lines to be wired between the routing prohibition regions,the minimum numbers being set again at step S13. In the case ofexceeding the values of the maximum numbers Lmax1 (the Y direction) andLmax2 (the X direction) (step S14: No), the flow proceeds to step S5,re-examination of the basic input information F011 is carried out.

FIG. 9 shows the area 601 of the case where the routing prohibitionregions 301 are generated by carrying out the processes from step S2 toS11 and where a first determination is carried out at step S11. Next,FIG. 10 shows the area 601 of the case where: it is determined that therouting error is not restored in FIG. 9 in the first determination atstep S11 (step S11: No) ; the routing prohibition regions 302 aregenerated by setting again the numbers of Lmin1 (the Y direction) andLmin2 (the X direction) of the wiring lines passing between the routingprohibition regions using the increment numbers Cnt1=1 (the Y direction)and Cnt2=0 (the X direction) at step S13; and then a seconddetermination is carried out at step S11. In FIG. 9, though Lmin isequal to one (Lmin=1), Lmin is re-set to two (Lmin=2) in FIG. 10.

In the same manner, FIG. 11 shows an example of the area 601 of the casewhere the third determination is carried out at step S11. Moreover, FIG.12 shows an example of the area 601 of the case where the fourthdetermination is carried out at step S11.

Referring to FIGS. 13 to 16, an example where: the routing prohibitionregion generating condition is changed at step S13 of FIG. 3B; it isdetermined at step S14 that the condition of the input information isnot satisfied; and the routing error is restored by re-examining theinput information, will be described next. Here, FIGS. 13 to 16 areschematic diagram describing the example where the routing error isrestored. In FIGS. 13 to 16, the area 601 includes wiring lines N6 toN42 and routing prohibition regions 305 and 306.

FIG. 13 shows the case where the routing prohibition regions 305 same asin FIG. 12 are generated at step S7 by setting: the generation ratePsnt1 of the routing prohibition region of the Y direction routing isequal to sixty (Psnt1=60); the minimum number Lmin1 of the wiring linesto be wired between the routing prohibition regions is four (Lmin1=4) ;the generation rate Psnt2 of the routing prohibition region of the Xdirection routing is equal to fifty (Psnt2=50); and the minimum numberLmin2 of the wiring lines to be wired between the routing prohibitionregions is one (Lmin2=1). That is, FIG. 13 shows the state after theprocesses that: the routing error is not restored at step S11 (step S11:No); the generation condition of the routing prohibition region ischanged at step S13; it is determined that the generation conditionsatisfies the condition of the input information at step S14; and thenthe processes of step S6 to step S10 are repeatedly carried out, whichis shown in each of FIGS. 9 to 11.

FIG. 13 shows a result obtained by: changing the generation condition ofthe routing prohibition region at step S13 because the routing error wasnot restored at step S11 in the arrangement of the routing prohibitionregion of FIG. 11; obtaining the arrangement of the routing prohibitionregion of FIG. 12; and then carrying out re-estimation of the outlinerouting in consideration of the routing prohibition regions 305 at stepS8. That is, FIG. 13 shows a state where the routing errors occurbecause three wiring lines N6, N7 and N8, three wiring lines N9, N10 andN11, three wiring lines N12, N13 and N14, three wiring lines N15, N16and N17, three wiring lines N18, N19 and N20, three wiring lines N21,N22 and N23, and three wirings lines N24, N25 and N26 are wired in onerouting track, respectively.

FIG. 14 shows a result obtained by: deleting the routing prohibitionregions 305 at step S9; extracting the wiring crowding degree again atstep S2; determining that there is no place with the high wiringcrowding degree at step S3 to proceed to step 10; and then carrying outthe detail routing. FIG. 14 shows a state where two wiring lines N7 andN8 and two wiring lines N23 and N24 are wired in one routing track,respectively. That is, the routing error still remains and thus it canbe determined that the routing error could not be restored at step S11.

Next, the routing prohibition region generation condition is changed atstep S12. Since the minimum number Lmin1 of the wiring lines to be wiredbetween the routing prohibition regions cannot be changed to be 4 ormore at the generation rate Psnt1=60 of the routing prohibition regionof the Y direction routing in FIG. 13 at step S14, it is determined thatthe condition of the input information is not satisfied. Therefore, theflow returns to step S5 to create the input information again.

Specifically, FIG. 14 is under the same routing prohibition regiongeneration condition as that of FIG. 12, and when the number Lmin1 (theY direction) of the wiring lines passing between the routing prohibitionregions is re-set up by setting the Cnt1 to one (Cnt1=1) in the Ydirection, Lmin1 is equal to five (Lmin1=5). Lmax1B is equal to 1.6(Lmax1B=1.6) based on Equation (3), and SLext1 is equal to 20(SLext1=20) based on Equation (5). Thus, the numbers become larger thanLext1=12 obtained by Equation (4), thereby not satisfying the conditionof the routing prohibition region generation rate of the information (c)of the basic input information F011. Accordingly, as the result of thedetermination at step S14, the flow proceeds to step S5 to change thecondition of the input information.

FIG. 15 is a diagram showing the state where: the input information iscreated again after returning to step S5; the generation rate Psnt1 ofthe routing prohibition region of the Y direction routing is changed;and then the routing prohibition regions 306 are generated. FIG. 15shows the case where the routing prohibition regions 306 are generatedat step S7 by changing the routing prohibition region generation rate ofthe Y direction routing from FIG. 13 to set: the generation rate Psnt1of the routing prohibition region of the Y direction routing to 75(Psnt1=75); the minimum number Lmin1 of the wiring lines to be wiredbetween the routing prohibition regions to one (Lmin1=1); the generationrate Psnt2 of the routing prohibition region of the X direction routingto 50 (Psnt2=50); and the minimum number Lmin2 of the wiring lines to bewired between the routing prohibition regions to one (Lmin2=1).

Next, a result of the re-estimation of the outline routing at step S8 inconsideration of the routing prohibition region will be described. FIG.15 shows a state where the routing errors occur because three wiringlines N28, N29 and N30, three wiring lines N31, N32 and N33, threewiring lines N34, N35 and N36, three wiring lines N37, N38 and N39, andthree wiring lines N40, N41 and N42 are wired in one routing track,respectively. In the same manner as the descriptions of FIGS. 13 and 14,as a result of carrying out the detail routing at step S10 after theflow proceeds to step S9, step S2 and step S3, the routing error isrestored by using the routing track reserved by arranging the routingprohibition region 306 as shown in FIG. 16.

In addition, in the above-mentioned example, the case is described inwhich the routing prohibition region generation information of the Ydirection routing is created to one place with the high wiring crowdingdegree. However, when the information (a) of the routing prohibitiongeneration region and the information (b) of the object wiring layer andthe like of the basic input information F011 are changed and whenrespective variables (Lmin, Psnt, Cnt, Lmax, La11, Lext, and SLext) ofthe respective Equations corresponding to the information are prepared,a plural pieces of output information (F02) can be created, and therouting prohibition region can be configured on the basis of theplurality of conditions at the same time at step S7 of FIG. 3A.

As described above, the layout method of the semiconductor integratedcircuit according to the embodiment of the present invention is carriedout.

The present invention is the layout method that extracts the wiringcrowding place after the placement of circuit elements and the routingof the semiconductor integrated circuit, generates the plurality ofrouting prohibition regions in an area including the wiring crowdingplace, carries out the routing by bypassing the plurality of the routingprohibition regions, deletes the plurality of routing prohibitionregions, and carries out the re-routing. The layout method includessteps of: calculating a size (a width and/or a length) and an intervalof the plurality of routing prohibition regions in consideration of thegeneration rate for generating the routing prohibition region in thearea in each wiring layer and outputting a calculation result as therouting prohibition region generation information, in the generation ofthe routing prohibition region; and generating the plurality of routingprohibition regions in the area including the wiring crowding place onthe basis of the routing prohibition region generation information.Specifically, routing resources can be dispersed to be reserved byarranging the plurality of routing prohibition regions in the wiringcrowding place in a scattering manner. In the case where the re-routingis carried out after the plurality of routing prohibition regions isdeleted, since the routing is carried out by using the separatelyarranged routing resources, a possibility that the wiring lines arecrowded can be lowered, thereby reducing the degree of the crowding evenif the wiring lines are crowded. As the result, a problem that therouting error remains after the detail routing and a problem that therouting error correction time is increased, caused by increase of therouting error due to the routing bypassing the routing prohibitionregion, can be solved.

The present invention has the above-mentioned features, and therebygenerating the routing prohibition region 301 at the minimum intervalLmin1 of the wiring lines to be wired between the routing prohibitionregions by using one grid width of the objective wiring layer as theminimum unit to the area 601 covering the wiring crowding place as shownin FIG. 9. Accordingly, the wiring crowding region is not entirely setto the routing prohibition as compared with the conventional technique.Thus, the minimum interval Lmin1 of the wiring lines to be wired betweenthe routing prohibition regions can be used as the routing region in thearea 601 after the generation of the routing prohibition regions 301.Then, the amount of wiring lines bypassing the area 601 in the outlinerouting at step S8 of FIG. 3A is smaller than that of the conventionalexample, the routing error between the bypassing wiring line and anotherwiring line can be reduced, and thus the number of routing errors can besuppressed, thereby shortening the routing error correction time incomparison with the conventional example.

The present invention is able to reduce the number of routing errors andshorten the routing error correction time. This is because: since therouting prohibition region is generated at the minimum interval of thewiring lines to be wired between the routing prohibition regions byusing the one grid width of the objective wiring layer to the wiringcrowding place, the wiring crowding region is not entirely set to therouting prohibition and the interval between the routing prohibitionregions can be used as the routing region, and accordingly the amount ofbypassing wiring lines is reduced, thereby reducing the routing errorbetween the bypassing wiring line and another wiring line.

It is apparent that the present invention is not limited to the aboveembodiment, but may be modified and changed without departing from thescope and spirit of the invention.

Although the present invention has been described above in connectionwith several exemplary embodiments thereof, it would be apparent tothose skilled in the art that those exemplary embodiments are providedsolely for illustrating the pre sent invention, and should not be reliedupon to construe the appended claims in a limiting sense.

1. A layout method of a semiconductor integrated circuit, comprising: extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements of said semiconductor integrated circuit is carried out; generating a plurality of routing prohibition regions where a routing is prohibited in an area including said wiring crowding place; carrying out a routing by bypassing said plurality of routing prohibition regions; deleting said plurality of routing prohibition regions after said carrying out routing step; and carrying out a re-routing after said deleting step, wherein said generating step includes: calculating a size and an interval of said plurality of routing prohibition regions based on a rate for generating a routing prohibition region in said area in each wiring layer, and generating said plurality of routing prohibition regions in said area on the basis of said calculating result.
 2. The layout method according to claim 1, wherein at least one of a width and a length of each of said plurality of routing prohibition regions in said calculating step is equal to a width of one routing track.
 3. The layout method according to claim 1, wherein said interval of each of said plurality of routing prohibition regions in said calculating step is equal to a width of one routing track.
 4. The layout method according to claim 1, wherein after said deleting step is performed, said extracting step to said deleting step are performed repeatedly, until said wiring crowding place disappears.
 5. The layout method according to claim 1, further comprising: determining whether a routing error is restored after said carrying out re-routing step; and changing said size and said interval of said plurality of routing prohibition regions if said routing error is not restored, wherein said changing step, said generating step to said carrying out re-routing step, and said extracting step are performed repeatedly, until said routing error is restored.
 6. The layout method according to claim 5, wherein at least one of a width and a length of each of said plurality of routing prohibition regions in said changing step is changed such that an incremental value equal to a width of one routing track is added.
 7. The layout method according to claim 5, wherein said interval of each of said plurality of routing prohibition regions in said changing step is changed such that an increment value equal to a width of one routing track is added.
 8. A tangible computer-readable medium including a computer program for a layout method of a semiconductor integrated circuit, comprising code operable to control a computer, the code comprising: extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements of said semiconductor integrated circuit is carried out; generating a plurality of routing prohibit ion regions where a routing is prohibited in an area including said wiring crowding place; carrying out a routing by bypassing said plurality of routing prohibition regions; deleting said plurality of routing prohibition regions after said carrying out routing step; and carrying out a re-routing after said deleting step, wherein said generating step includes: calculating a size and an interval of said plurality of routing prohibition regions based on a rate for generating a routing prohibition region in said area in each wiring layer, and generating said plurality of routing prohibition regions in said area on the basis of said calculating result.
 9. The tangible computer-readable medium according to claim 8, wherein at least one of a width and a length of each of said plurality of routing prohibition regions in said calculating step is equal to a width of one routing track.
 10. The tangible computer-readable medium according to claim 8, wherein said interval of each of said plurality of routing prohibition regions in said calculating step is equal to a width of one routing track.
 11. The tangible computer-readable medium according to claim 8, wherein after said deleting step is performed, said extracting step to said deleting step are performed repeatedly, until said wiring crowding place disappears.
 12. The tangible computer-readable medium according to claim 8, further comprising: determining whether a routing error is restored after said carrying out re-routing step; and changing said size and said interval of said plurality of routing prohibition regions if said routing error is not restored, wherein said changing step, said generating step to said carrying out re-routing step, and said extracting step are performed repeatedly, until said routing error is restored.
 13. The tangible computer-readable medium according to claim 12, wherein at least one of a width and a length of each of said plurality of routing prohibition regions in said changing step is changed such that an incremental value equal to a width of one routing track is added.
 14. The tangible computer-readable medium according to claim 12, wherein said interval of each of said plurality of routing prohibition regions in said changing step is changed such that an increment value equal to a width of one routing track is added.
 15. A layout device of a semiconductor integrated circuit, comprising: a crowding extraction and determination portion configured to extract a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements of said semiconductor integrated circuit is carried out; a prohibition region generating portion configured to generate a plurality of routing prohibition regions where a routing is prohibited in an area including said wiring crowding place; a routing re-estimation portion configured to carry out a routing by bypassing said plurality of routing prohibition regions; a prohibition region deletion portion configured to delete said plurality of routing prohibition regions after said routing by bypassing is carried out; and a re-routing portion configured to carry out a re-routing after said plurality of routing prohibition regions is deleted, wherein said prohibition region generating portion includes: a prohibition region calculating portion configured to calculate a size and an interval of said plurality of routing prohibition regions based on a rate for generating a routing prohibition region in said area in each wiring layer, and a prohibition region generating portion configured to generate said plurality of routing prohibition regions in said area on the basis of said calculating result.
 16. The layout device according to claim 15, wherein at least one of a width and a length of each of said plurality of routing prohibition regions, calculated by said prohibition region calculating portion, is equal to a width of one routing track.
 17. The layout device according to claim 15, wherein said interval of each of said plurality of routing prohibition regions, calculated by said prohibition region calculating portion, is equal to a width of one routing track.
 18. The layout device according to claim 15, wherein after said prohibition region deletion portion deletes said plurality of routing prohibition regions, said crowding extraction and determination portion, said prohibition region generating portion, said routing re-estimation portion and said prohibition region deletion portion are operated repeatedly, until said wiring crowding place disappears.
 19. The layout device according to claim 15, further comprising: an error determination portion configured to determine whether a routing error is restored after said re-routing is carried out; and a prohibition region changing portion configured to change said size and said interval of said plurality of routing prohibition regions if said routing error is not restored, wherein said prohibition region changing portion, said prohibition region generating portion, said routing re-estimation portion, said prohibition region deletion portion, said re-routing portion, and said crowding extraction and determination portion are operated repeatedly, until said routing error is restored.
 20. The layout device according to claim 19, wherein at least one of a width and a length of each of said plurality of routing prohibition regions, changed by said prohibition region changing portion, is changed such that an incremental value equal to a width of one routing track is added.
 21. The layout device according to claim 19, wherein said interval of each of said plurality of routing prohibition regions, changed by said prohibition region changing portion, is changed such that an increment value equal to a width of one routing track is added. 